The present invention relates to a structure of an element isolation region in a semiconductor device and a semiconductor device manufacturing method.
In a semiconductor device having silicon as its main constituent, an element isolation region (hereafter referred to as a field area) is formed through the LOCOS (local oxidation of silicon) method or the STI (shallow trench isolation) method to electrically isolate elements in the prior art. An area other than the field area is referred to as an active area, and the elements are formed in the active area. When a field area is formed through the LOCUS method, a bird's beak is formed at an end of the field area, reducing the size of the area that can be utilized as active area. With further miniaturization of elements achieved in recent years, the width and the pitch of the active area have become smaller and the use of the LOCOS method to form the field area is problematic. In contrast, the STI method, which by its nature creates hardly any bird's beak, is considered to be a more viable method of field area formation, achieving reduced conversion difference. FIG. 7 illustrates the STI manufacturing method. As shown in FIG. 7(a), a groove referred to as a trench 7 is formed at a Si substrate 1. Then, as illustrated in FIG. 7(b), a trench liner oxide film 71 is formed at the insidewalls of the trench 7 and the trench is filled with an embedded insulating film 72 such as a CVD oxide film to form a field area.
However, when the field area is formed by adopting the manufacturing method described above, a groove referred to as a divot 81, as shown in FIG. 8, is formed at the surface of the field area near the boundary with the active area. As a result, the edge of the active area adjacent to the divot 81 becomes exposed. FIG. 8 is an enlarged view of the area around the edge. When this area becomes exposed, numerous problems arise with regard to the occurrence of stress which is to be detailed later.
When a field area is formed through the STI method, the embedded insulating film 72 and the Si substrate 1 become expanded during the heat treatment performed after the trench is filled with the embedded insulating film 72. Since the embedded insulating film 72 and the Si substrate 1 have different coefficients of expansion, stress occurs at their interface. In addition, stress also occurs at the interface of the trench liner oxide film 71 formed through thermal oxidation and the Si substrate 1 as a result of volumetric expansion caused by the oxygen atoms occupying space between the Si atoms. These stresses occur near the boundary of the active area and the field area, and a particularly intense stress occurs at the edges of the active area.
At the edge of an area of intense stress, accelerated diffusion of impurities occurs during the annealing process implemented after the impurity ion implantation and, as illustrated in FIG. 8, the impurity concentration at the edge becomes lowered compared to that around the center of the active area. If the edge becomes exposed as a result of divot formation, a parasitic transistor with a low threshold voltage is formed over the area with a low impurity concentration. In such a case, there will be a kink in the characteristics curve achieved by the transistor, as shown in FIG. 9. In FIG. 9, the vehicle axis represents the drain current Id and the horizontal axis represents the gate voltage Vg. If there is no parasitic transistor present, the transistor characteristics curve is free of any kink. The presence of a kink results in electrical characteristics different from the design electrical characteristics, and thus, the transistor characteristics cannot be identified. In addition, since parasitic transistors and kinks manifesting under these circumstances are not uniform, the transistor characteristics cannot be determined with uniformity during the production, which, in turn, results in inconsistency in transistor characteristics.
Furthermore, occurrence of stress induces a dislocation, resulting in the formation of crystal defects. When the impurity concentration is reduced, a depletion layer is more readily extended compared to the other areas, to lead to an increase in the junction leak current of via the crystal defects.
An oxide film is not formed at the Si substrate isotropically and the direction in which the oxide film is formed varies depending upon the direction of the crystal. If the edge of the active area is exposed due to the formation of a divot, the thickness of the oxide film formed at the surface along the vertical direction of the edge becomes different from the thickness of the oxide film formed at the surface along the horizontal direction. The combination of this inconsistent oxide film thickness and the stress occurring at the edge causes the thickness of a gate oxide film 92 to become locally reduced over this area, as shown in FIG. 8. When the film thickness is reduced, the reliability of the gate oxide film 92 becomes an issue. In addition, the structure of this area is such that an electric field tends to concentrate in the area in the first place, and if the gate oxide film 92 becomes thinner over the area, more electric field concentrates through a synergistic effect. An electric field concentration is considered to be one of the causes of kinks and is, therefore, not desirable.